6.4 Simultaneous Statements

We use simultaneous statements in VHDL-AMS to express the equations that govern the analog behavior of a model. The simultaneous statements express explicit differential and algebraic equations that, together with implicit equations derived from the model structure and interconnections, constrain the values of quantities in a model. Simultaneous statements can appear anywhere a concurrent statement is allowed. This is shown by an augmented syntax rule for architecture bodies:

architecture_body <span class="unicode">?</span>     <b class="bold">architecture</b> identifier <b class="bold">of</b> <i class="emphasis">entity_</i>name <b class="bold">is</b>         { block_declarative_item}<a name="522"></a><a name="IDX-218"></a>   <b class="bold">begin</b>       { concurrent_statement  simultaneous_statement }   <b class="bold">end</b> [ <b class="bold">architecture</b> ] [ identifier ] ;

Thus, we can use simultaneous statements along with processes to express both analog and digital behavior within an architecture body. The simultaneous statements contain expressions, as we have seen in other VHDL-AMS statements, but the results of expressions in simultaneous statements are interpreted differently. They are used to constrain the values of quantities rather than to provide new values for objects.

There are five kinds of simultaneous statement in VHDL-AMS: simple simultaneous statements, simultaneous if statements, simultaneous case statements, simultaneous null statements and simultaneous procedural statements. We discuss the first four kinds of simultaneous statement in this section; we defer simultaneous procedural statements until Chapter 9, where we discuss subprograms.