Many digital systems can be implemented as regular iterative compositions of subsystems. Memories are a good example, being composed of a rectangular array of storage cells. Indeed, VLSI designers prefer to find such implementations, as they make it easier to produce a compact, area-efficient layout, thus reducing cost. If a design can be expressed as a repetition of some subsystem, we should be able to describe the subsystem once, then describe how it is to be repeatedly instantiated, rather than describe each instantiation individually. In this chapter, we look at the VHDL-AMS facility that allows us to generate such regular structures.

17.1 Generating Iterative Structures

We have seen how we can describe the implementation of a subsystem using simultaneous statements, as well as concurrent statements such as processes and component instantiations. If we want to replicate a subsystem, we can use a generate statement. This is a concurrent statement containing further concurrent and simultaneous statements that are to be replicated. Generate statements are particularly useful if the number of times we want to replicate the concurrent statements is not fixed but is determined, for example, from the value of a generic constant. The syntax rule for writing iterative generate statements is

generate_statement <span class="unicode">?</span>    <i class="emphasis">generate</i>_label :    <b class="bold">for</b> identifier <b class="bold">in</b> discrete_range <b class="bold">generate</b>         [ { block_declarative_item }    <b class="bold">begin</b> ]         { concurrent_statement...