The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling

The package declarations for the IEEE standard multivalue logic and mathematical packages are listed in this appendix. The IEEE standards also include package bodies defining the detailed meaning of each of the operators and functions provided by the packages. However, simulator vendors are allowed to substitute accelerated implementations of the packages rather than compiling the package bodies into simulations. The IEEE standards require the packages to be in a resource library named ieee.
<b class="bold">package</b> std_logic_1164 <b class="bold">is</b> <b class="bold">------------------------------------------------------------------------</b> -- <i class="emphasis">logic state system (unresolved)</i> ------------------------------------------------------------------------ <b class="bold">type</b> std_ulogic <b class="bold">is</b> ('U', -- <i class="emphasis">Uninitialized</i> 'X', -- <i class="emphasis">Forcing Unknown</i> '0', -- <i class="emphasis">Forcing 0</i> '1', -- <i class="emphasis">Forcing 1</i> 'Z', -- <i class="emphasis">High Impedance</i> ...