The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
From the Old to the New
This book as been updated so that the new features of IEEE Std. 1364-2001 are always used even though the "old ways" of writing Verilog (i.e. IEEE Std. 1364-1995) are still valid. In this preface, we show a few side-be-side examples of the old and new. Thus, this section can stand as a short primer on many of the new changes, or as a reference for how to read "old code." Throughout this preface, cross references are made to further discussion in the earlier parts of the book. However, not all changes are illustrated in this preface.
Ports, Sensitivity Lists, and Parameters
Port declarations can now be made in "ANSI C" style as shown in Example P.1. In the old style, the port list following the module name could only contain the identifiers; the actual declarations were done in separate statements. Additionally, only one declaration could be made in one statement. Now, the declarations can be made in the opening port list and multiple declarations can be made at the same time. Multiple declarations are illustrated in the declaration of eSeg being an "output reg" in the new standard; previously this took two statements as shown on the right of the example (See Section 5.1). This style of declaration also applies to user defined primitives (See chapter 9). These two module descriptions are equivalent.
Example P.1: 2001 Standard (Left); Previous 1995 (Right)
<a name="10"></a><a name="IDX-xviii"></a>module binary ToESeg_Behavioral (output reg eSeg, input ...
Copyright Springer Science+Business Media. Inc. 2002 under license agreement with Books24x7
