The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
2.4: Inferring Sequential Elements
2.4 Inferring Sequential Elements
Sequential elements are the latches and flip flops that make up the storage elements of a register-transfer level system. Although they are a fundamental component of a digital system, they are difficult to describe to a synthesis tool; the main reason being that their behavior can be quite intricate. The form of the description of some of these elements (especially flip flops) are almost prescribed so that the synthesis tool will know which library element to map the behavior to.
2.4.1 Latch Inferences
Latches are level sensitive storage devices. Typically, their behavior is controlled by a system wide clock that is connected to a gate input ( G). While the gate is asserted (either high or low), the output Q of the latch follows the input D it is a combinational function of D. When the gate is unasserted, the output Q remembers the last value of the D input. Sometimes these devices have asynchronous set and/or reset inputs. As we have seen in section 2.3.2, latches are not explicitly specified. Rather, they arise by inference from the way in which a description is written. We say that latches are inferred. One example of an inferred latch was shown in Example 2.7.
Latches are inferred using the always statement as a basis. Within an always statement, we define a control path to be a sequence of operations performed when executing an always loop. There may be many different...
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