The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Chapter 8: Advanced Timing
The previous chapters were based on a relatively straight-forward understanding of how the Verilog simulator schedules and executes events. This chapter develops a more detailed model of the simulator, including the processing of a number of the more subtle timing semantics of the language. Topics include the simulator scheduling algorithm, non-deterministic aspects of the language, and non-blocking assignments.
The material in this chapter is meant to explain conceptually how Verilog simulators are expected to work. However, the presentation may not match any particular implementation. There are plenty of short-cuts, tricks, and go-fasts that are or could be implemented. Their mileage and software-engineering appropriateness may vary and are not the topic of the chapter.
8.1 Verilog Timing Models
A hardware description language is used to model both the function and timing of digital systems. The simulation of these models is organized around events. An event is a change in a value in the simulation model at a specific time. The semantics of the language specify how an event causes other events to occur in time. Through this sequence of events, simulation models are executed, and simulation time is advanced. A timing model is a model of how simulation time is advanced it is tied closely to the semantics of the hardware description language. So far, we have seen two timing models used by the Verilog language. These timing models are illustrated by gate level and behavioral level descriptions.
A simulation model should not be confused with a timing model
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