The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Chapter 3: Behavioral Modeling
We now begin a more in-depth discussion of the constructs used to model the behavior of digital systems. These have been split into two groups. The first are statements that are, for the most part, similar to those found in programming languages: if-thenelse, loops, etc. In the next chapter we take up the statements that are oriented toward modeling the concurrent nature of digital hardware.
3.1 Process Model
The basic essence of a behavioral model is the process. A process can be thought of as an independent thread of control, which may be quite simple, involving only one repeated action, or very complex. It might be implemented as a sequential state machine, as an asynchronous clearing of a register, or as a combinational circuit. The point is that we conceive the behavior of digital systems as a set of these independent, but communicating, processes. Their actual implementation is left to the context of the description (what level of abstraction we are dealing with) and the time and area constraints of the implementation.
The basic Verilog statement for describing a process is the always construct:
always_construct ::= always statement
The always continuously repeats its statement, never exiting or stopping. A behavioral model may contain one or more always statements. If a module contains none, it is purely a specification of hierarchical structure instantiated submodules and their interconnections.
The initial construct is similar to the always...
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