The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Appendix F: System Tasks and Functions
In this section we present some of the built in Verilog System Tasks and Functions. Our philosophy for this book is not to become a substitute for the simulator manual. Rather, we want to illustrate a few of the basic methods of displaying the results of simulation, and stopping the simulation.
F.1 Display and Write Tasks
There are two main tasks for printing information during a simulation: $display and $write. These two are the same except that $display always prints a newline character at the end of its execution. Examples of the $display task were given throughout the main portion of the book. A few details will be given here.
The typical form of the parameters to these tasks is
$display ("Some text %d and maybe some more: %h.", a, b); This statement would print the quoted string with the value of a substituted in for the format control "%d", and b is substituted in for the format control "%h". The "%d" indicates that the value should be printed in a decimal base. %h specifies hexadecimal.
Allowable letters in the format control specification are:
| h or H | display in hexadecimal |
| d or D | display in decimal |
| o or O | display in octal |
| b or B | display in binary |
| c or C | display ASCII character |
| v or V | display net signal strength (see Table 10.4). |
| m or M | display hierarchical name |
| s or S | display string |
Using the construct "%0d" will print a decimal number...
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