The Verilog Hardware Description Language, Fifth Edition

Appendix E: Registers, Memories, Integers, and Time

E.1 Registers

Registers are abstractions of storage devices found in digital systems. They are defined with the reg keyword and are optionally given a size (or bit width). The default size is one. Thus:

    reg  tempBit;

defines a single bit register named tempBit, while

    reg  [15:0]  tempNum;

defines a 16-bit register named tempNum. Single-bit registers are termed scalar, and multiple-bit registers are termed vector. The bit width specification gives the name of the most significant bit first (in this case, 15) and the least significant bit last.

The register could have been declared as

    reg  [0:15]  tempNum;

with the only difference being that the most significant bit is named (numbered) 0. Of course, all the other bits are differently numbered. Further, the register can be declared as signed

<a name="747"></a><a name="page330"></a>    reg  signed  [15:0]  tempNum;

indicating that when used in an expression, it is to be treated as a signed (2's complement) number.

The general form of a register specification is:

reg_declaration ::= <b class="bold">reg [signed]</b> [range] list_of_variable_identifiers;list_of_variable_identifiers ::= variable_type { , variable_type }variable_type       ::= variable_identifier [ = constant_expression]          variable_identifier dimension  {dimension}variable_identifier       ::= identifierdimension       ::= [dimension_constant_expression : dimension_constant_expression ]

Either a single bit, or several contiguous...

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