The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Chapter 10: Switch Level Modeling
Designs at the logic level of abstraction, describe a digital circuit in terms of primitive logic functions such as or, and nor, etc., and allow for the nets interconnecting the logic functions to carry 0,1, x and z values. At the analog-transistor level of modeling, we use an electronic model of the circuit elements and allow for analog values of voltages or currents to represent logic values on the interconnections.
The switch level of modeling provides a level of abstraction between the logic and analog-transistor levels of abstraction, describing the interconnection of transmission gates which are abstractions of individual mos and cmos transistors. The switch level transistors are modeled as being either on or off, conducting or not conducting. Further, the values carried by the interconnections are abstracted from the whole range of analog voltages or currents to a small number of discrete values. These values are referred to as signal strength.
10.1 A Dynamic MOS Shift Register Example
We began our discussion of logic level modeling in Chapter 6 by listing the primitive set of gates provided by the Verilog language (the list is reproduced as Table 10.1). At the time, only the logic level primitives were discussed. We can see from the switch level primitives, shown in the right three columns of the table, that they all model individual Mosfavios transistors.
| n_input gates | n_output gates | tristate gates | pull gates | MOS switches | bidirectional switches |
|---|---|---|---|---|---|
| and | buf | bufif0 | pullup | nmos | tran |
| nand |
Copyright Springer Science+Business Media. Inc. 2002 under license agreement with Books24x7
