The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
2.8: Summary on Logic Synthesis
2.8 Summary on Logic Synthesis
We have seen that descriptions used for logic synthesis are very stylized and that some of the constructs are overloaded with semantic meaning for synthesis. In addition, there are several constructs that are not allowed in a synthesizable description. Because these can vary by vendor and version of the tool, we chose not to include a table of such constructs. Consult the user manual for the synthesis tool you are using.
Table 2.1 summarizes some of the basic rules of using procedural statements to describe combinational logic and how to infer sequential elements in a description.
| Type of Logic | Output Assigned To | Edge Specifiers in Sensitivity List |
|---|---|---|
| Combinational | An output must be assigned to in all control paths. | Not allowed. The whole input set must be in the sensitivity list. The construct @(*) assures this. |
| Inferred latch | There must exist at least one control path where an output is not assigned to. From this "omission," the tool infers a latch. | Not allowed. |
| Inferred flip flop | No affect | Required from the presence of an edge specifier, the tool infers a flip flop. All registers in the always block are clocked by the specified edge. |
Listing 2.28: FSM For the Datapath
<a name="186"></a><a name="IDX-67"></a> module fsm (input LT, LEQ, ck, reset, ...
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