The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Chapter 9: User-Defined Primitives
Verilog provides a set of 26 gate level primitives for modeling the actual logic implementation of a digital system. From these primitives, presented in Chapter 6, larger structural models may be hierarchically described. This chapter presents an advanced method for extending the set of gate level primitives to include user-defined combinational, and level- and edge-sensitive sequential circuits.
There are several reasons for wanting to extend the set of gate level primitives. First, user-defined primitives are a very compact and efficient way of describing a possibly arbitrary block of logic. Secondly, it is possible to reduce the pessimism with respect to the unknown x value in the simulator's three valued logic, thus creating more realistic models for certain situations. Finally, simulation efficiency may be gained through their use. Note, however, that these may not be used to specify designs for logic synthesis.
9.1 Combinational Primitives
9.1.1 Basic Features of User-Defined Primitives
As shown in Example 9.1, user-defined primitives are defined in a manner similar to a truth table enumeration of a logic function. Primitives are defined at the same lexical level as modules. i.e. primitives are not defined within modules. This example describes a primitive for generating the carry out of a single-bit full adder. carry-Out is the output, and carryIn, aIn, and bIn are the inputs. A table is then specified showing the value of the output for the various combinations of the inputs. A colon separates the output on its right from the inputs on its...
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