The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
2.3: Procedural Statements to Specify Combinational Logic
2.3 Procedural Statements to Specify Combinational Logic
In addition to using continuous assign statements and primitive gate instantiations to specify combinational logic, procedural statements may be used. The procedural statements are specified in an always statement, within a task called from an always statement, or within a function called from an always statement or a continuous assign. In spite of the fact that a description using procedural statements appears sequential, combinational logic may be specified with them. Section 1.2 introduced this approach to specifying combinational logic. This section covers the topic in more detail.
2.3.1 The Basics
The basic form of a procedural description of combinational logic is shown in Example 2.4. It includes an always statement with an event statement containing all of the input variables to the combinational function. The example shows a multiplexor described procedurally. In this case, input a selects between passing inputs b or c to output f. Even though f is defined to be a register, a synthesis tool will treat this module as a specification of combinational logic.
Listing 2.4: Combinational Logic Described With Procedural Statements
module synCombinationalAlways (output reg f, input a, b, c); always @ (a, b, c) if (a == 1) ...
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