The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Chapter 7: Cycle-Accurate Specification
We now turn our attention to a higher level of modeling: cycle accurate, sometimes called scheduled behavior. At this level, a system is described in a clock-cycle by clock-cycle fashion, specifying the behavior that is to occur in each state. The term cycle-accurate is used because the values in the system are specified to be valid only at the time of the system's state change at a clock edge. This chapter presents the cycle-accurate method of specification, overviews behavioral synthesis, and illustrates how to specify systems for design using behavioral synthesis.
7.1 Cycle-Accurate Behavioral Descriptions
7.1.1 Specification Approach
Scheduled behavior is specified using always blocks, and "@(posedge clock);" statements are used to break the specification into clock cycles or states. Example 7.1 illustrates a scheduled behavioral description of a simple calculation. The module has ports for registers x, y, and the clock. Register i, a loop counter, is only used inside the module.
Using the cycle-accurate style of description, an "@(posedge clock);" statement is followed by behavioral statements and then by another "@(posedge clock)" statement. We'll call this "@(posedge clock)" the clock event. The statements between the two clock events constitute a state. The clock event statements need not appear in pairs; if there is only one clock event statement in a loop body, then the loop executes in one state and the next clock event is, indeed, itself.
In Example 7.1, consider state C, the last clock event and the statement that follows...
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