The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Appendix G: Formal Syntax Definition
This formal syntax specfication is provided in BNF. This information, starting in section G.2 and continuing through the end of this sppendix, is reprinted from IEEE Standard 1364-2001 "IEEE Standard Verilog Hardware Description Language Reference Manual (LRM)", Copyright 2001 by the Institute of Electrical and Electronics Engineers, Inc (IEEE). The IEEE disclaims any responsibility or liability resulting from the placement and use in this publication. This information is reprinted with the permission of the IEEE.
G.1 Tutorial Guide to Formal Syntax Specification
The formal syntax notation will be introduced through an example in this case Example G.1, an edge triggered D flip flop, dEdgeFF. Using this example we will describe the formal syntax of a module definition.
To this point, we have, by example, demonstrated that a module definition uses certain keywords ("module", "endmodule") and has other entities associated with it ("ports", "instantiations", etc.). The formal syntax for a module is:
<a name="769"></a><a name="IDX-340"></a>module_declaration ::= module_keyword module_identifier [ module_parameter_port_list] [list_of_ports]; { module_item } <b class="bold">endmodule</b> module_keyword module_identifier [ module_parameter_port_list] [list_of_ports_declarations]; { non_port_module_item } <b class="bold">endmodule</b>module_keyword <b class="bold">::= module</b> ...
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