2.1

In section 2.2 on page 37, we state that a synthesis tool is capable, and possibly constrained, to implement the functionality using different gate primitives. Explain why it might be "constrained" to produce an alternate implementation.

2.2

Alter the description of Example 2.7 so that there is no longer an inferred latch. When a is not one, b and c should be OR-d together to produce the output.

2.3

Alter the description of Example 2.16. Use a case statement to infer the latch.

2.4

Why can't while and forever loops be used to specify combinational hardware?

2.5

Rewrite Example 2.21 as a Moore machine. An extra state will have to be added.

2.6

Rewrite Example 2.21 using a one-hot state encoding. Change the description to be fully parameterized so that any state encoding may be used.

2.7

Write a description for the FSM shown in Figure 2.7 with inputs Ain, Bin, Cin, clock, and reset, and output Y.

Figure 2.7: Control Over Synthesis

1. A single always block

2. Two always blocks; one for the combinational logic and the other for the sequential.

3. Oops, this circuit is too slow. We can't have three gate delays between the flip flop outputs and inputs; rather only two. Change part B so that Y is a combinational output. i.e. Move the gate generating d2 to the other side of the flip flops.

4. Simulate all of the above to...