The Verilog Hardware Description Language, Fifth Edition

Appendix C: Verilog Operators

C.1 Table of Operators

Table 3.1: Verilog Operators

Operator Symbol

Name

Definition

Comments

{,}

Concatenation

Joins together bits from two or more comma-separated expressions

Constants must be sized. Alternate form uses a repetition multiplier, {b, {3 {a, b}}} is equivalent to {b, a, b, a, b, a, b}.

+

Addition

Sums two operands.

Register and net operands are treated as unsigned. Real and integer operands may be signed. If any bit is unknown, the result will be unknown.

?

Subtraction

Finds difference between two operands.

Register and net operands are treated as unsigned. Real and integer operands may be signed. If any bit is unknown, the result will be unknown.

?

Unary minus

Changes the sign of its operand

Register and net operands are treated as unsigned. Real and integer operands may be signed. If any bit is unknown, the result will be unknown.

*

Multiplication

Multiply two operands.

Register and net operands are treated as unsigned. Real and integer operands may be signed. If any bit is unknown, the result will be unknown.

/

Division

Divide two operands

Register and net operands are treated as unsigned. Real and integer operands may be signed. If any bit is unknown, the result will be unknown. Divide by zero produces an x.

%

Modulus

Find remainder

Register and net operands are treated as unsigned. Real and integer operands may be signed. If any bit is unknown, the result will be unknown.

**

Power

Raise to the power of

Result = base...

UNLIMITED FREE
ACCESS
TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Category: Arithmetic Logic Units (ALU)
Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.