The Verilog Hardware Description Language, Fifth Edition
A valuable resource for engineers and students interested in modeling digital systems, this book takes a tutorial approach to presenting the major features of the language and its constructs.
TABLE OF CONTENTS The Verilog Hardware Description Language, Fifth Edition
Chapter 6: Logic Level Modeling
To this point, we have concentrated mostly on behavioral modeling of a digital system. Behavioral models are more concerned with describing the abstract functionality of a module, regardless of its actual implementation. Logic level modeling is used to model the logical structure of a module, specifying its ports, submodules, logical function, and interconnections in a way that directly corresponds to its implementation. This chapter presents the Verilog constructs that allow us to describe the logical function and structure of a system.
6.1 Introduction
There are several approaches to the logic level modeling of a digital system. Each of these approaches represents a sublevel of logic level modeling, and emphasizes different features of a module.
A gate level model of a circuit describes the circuit in terms of interconnections of logic primitives such as AND, OR, and XOR. Modeling at this level allows the designer to describe the actual logic implementation of a design in terms of elements found in a technology library or databook and thus be able to accurately analyze the design for such features as its timing and functional correctness. Since gate level modeling is so pervasive, the Verilog language provides gate level primitives for the standard logic functions.
A more abstract means of describing the combinational logic of a design is provided by the continuous assignment statement. This approach allows for logic functions to be specified in a form similar to Boolean algebra. The continuous assignment statement typically describes the behavior of a combinational...
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