Overview

Leakage power dissipation grows with every generation of CMOS process technology. This leakage power is not only a serious challenge to battery powered or portable products but increasingly an issue that has to be addressed in tethered equipment such as servers, routers, and set-top boxes.

To reduce the overall leakage power of the chip, it is highly desirable to add mechanisms to turn off blocks that are not being used. This technique is known as power gating.

Section two describes power gating from an RTL design perspective. This chapter provides an overview of power gating. The following chapters continue with descriptions of how to implement power gating at the RTL level, the power gating strategies used on the SALT chip, and the architectural implications of power gating. Our focus is how RTL designers can design power gating implementations in as technology-independent and portable a manner as possible.

4.1 Dynamic and Leakage Power Profiles

The basic strategy of power gating is to provide two power modes: a low power mode and an active mode. The goal is to switch between these modes at the appropriate time and in the appropriate manner to maximize power savings while minimizing the impact to performance.

The power reduction techniques described in chapter 2 do not affect the functionality of the design and do not require changes to the RTL. They can be handled fairly transparently from a design and implementation and perspective; power gating is more invasive than clock-gating in that it affects inter-block...