Low Power Methodology Manual: For System-on-Chip Design
Taking a practical approach, rather than a theoretical approach, this book describes a number of the techniques designers can use to reduce the power consumption of complex SoC designs.
TABLE OF CONTENTS Low Power Methodology Manual: For System-on-Chip Design
Chapter 13: Retention Register Design
For those designs that require fast resumption of operation after wakeup, it is necessary to save the current state of a design before going into sleep mode and to restore the state at wakeup. In this chapter, we describe on-chip retention methods, including retention registers and retention techniques for memory.
13.1 Retention Registers
There are a number of different retention register designs. The ones we discuss here are all variations of a standard scan-testable D-type flip-flop. We describe three kings of retention registers:
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Single Pin Live Slave uses a single save/restore control pin with minimal changes to the flop itself
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Single Pin Balloon uses a single save/restore control pin but adds a second slave latch for retention
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Dual Pin Balloon uses separate save and restore control pins and a second slave latch for retention
13.1.1 Single Pin "Live Slave" Retention Registers
The simplest form of retention register is one in which the underlying master-slave latch structure is adapted to provide a low-leakage mode to maintain the state of the slave latch.
Figure 13-1 shows the conceptual adaptation of the rising-edge clocked scan-register design.
Figure 13-1: Retention Register "Live Slave"
The front-end of the register is a multiplexer. When the scan-enable control "SE" is de-asserted it selects the functional data "D" input; when SE is asserted it selects the scan chain serial input "SI." To provide best setup timing behavior this mux and much of the data path use Low-V T transistors indicated in the drawing...
Copyright Synopsys, Inc. & ARM Limited 2007 under license agreement with Books24x7
