Low Power Methodology Manual: For System-on-Chip Design
Taking a practical approach, rather than a theoretical approach, this book describes a number of the techniques designers can use to reduce the power consumption of complex SoC designs.
TABLE OF CONTENTS Low Power Methodology Manual: For System-on-Chip Design
Glossary
- Power Domain
- A collection of design elements that share a single primary supply connection and, at least conceptually, share a common power strategy.
- Isolation
- Isolation is a technique for controlling the behavior of a signal that is driven by a powered down power domain. Isolation consists of driving the signal to a known state - 1, 0, or latching it to a previous value when the power domain is powered down.
- Retention
- Retention is a technique for retaining the state value of registers in a powered down power domain.
- Isolation Cells
- Cells (gates) that perform the isolation function in a design. Also knows as clamp cells or clamps.
- Level Shifters
- Cells (typically buffers) that translate inputs with one voltage swing to an output with a different voltage swing.
- Retention Register
- A register than extends the functionality of a normal register (flip-flop) with the ability to retain its memory during power down, assuming an appropriate second (always on) supply as well as save and restore signaling.
- Shadow Register
- The section of a retention register retains the register state during power down. Also known as a balloon registers (due to the topology of some implementations).
- Power Switch
- At the RTL and architectural level, a power switch allows the power to a power domain to be switched on or off (also known as power gated).
- Switching Network
- Physically, the power switch is implemented as a switching network of transistors. Also known as a switching fabric.
- Switching Transistor
- The individual switching transistor that...
Copyright Synopsys, Inc. & ARM Limited 2007 under license agreement with Books24x7
