Overview

A sleep transistor is either a pMOS or nMOS high V _T transistor and is used as a switch to shut off power supplies to parts of a design in standby mode. The pMOS sleep transistor is used to switch VDD supply and hence is called a "header switch." The nMOS sleep transistor controls VSS supply and hence is called a "footer switch." In designs at 90nm and below, either a header or footer switch is used due to tight voltage margin and too large area penalty when both header and footer switches are implemented.

Although the concept of the sleep transistor is straight forward, optimal sleep transistor design and implementation are a challenge due to various effects, introduced by the sleep transistor and its implementations, on design performance, area, routability, overall power dissipation, and signal/power integrity.

Optimal sleep transistor design also depends on design specific goals and chosen CMOS technology and process. A number of decisions need to be made including the choice of header or footer switch, normal or reverse body bias, optimal transistor size, and layout implementation details such as single or double row and extra rail or direct via-pillar for permanent power connection.

This chapter is written as a guide to the advantages and trade-offs associated with different choices, rather than the design procedure which is well understood by the transistor designers. The investigations of various sleep transistor characteristics in the power-gating design context are based on SPICE analysis instead of the theories and...