Overview

One of the first steps in implementing a low power design is to select a library of standard cells and a set of memory compilers that support the low power strategy used in the design.

This chapter describes the requirements for standard cell libraries and memories for a multi-voltage, power gated design.

12.1 Standard Cell Libraries

Standard cell libraries are tuned for different performance, power and area goals. For low-power design the choice and mix of libraries may have a significant impact on power, timing and area.

One key characteristic of a cell library is cell height. Cell height is measured in tracks, which is the metal one (M1) pitch. An 8-track cell is tall enough that eight horizontal M1 wires can run through it.

Cell libraries are designed to a certain number of tracks in height, and this height affects the timing and routing characteristics of the library:

• Tall track height libraries support more complex routing, larger drive strength transistors and typically are tuned for performance but may exhibit higher leakage power. An 11 or 12-track library is considered a tall track height library.

• Low-track height libraries are optimized for area efficiency, but generally are designed with smaller, lower drive strength transistors so are less appropriate for high-speed designs. A 7 or 8-track library is considered a low track height library.

• Standard track height libraries are designed to give a reasonable trade-off between area efficiency and performance. These libraries are used in the majority of designs. A...