Low Power Methodology Manual: For System-on-Chip Design
Taking a practical approach, rather than a theoretical approach, this book describes a number of the techniques designers can use to reduce the power consumption of complex SoC designs.
TABLE OF CONTENTS Low Power Methodology Manual: For System-on-Chip Design
11.3: Synthesis
11.3 Synthesis
Logic synthesis is the process by which we map a generic RTL representation of the design to a target technology. In low power designs, we include the power intent the specification of power domains, isolation, and so on at synthesis so that optimization includes the effects of these added circuits. We can view the logic synthesis of a multi-voltage power gated design as simply a low power overlay to the typical logic synthesis process.
11.3.1 Power Intent
This power intent describes the power domains in the design and defines how power is distributed to the various power domains. It defines where level shifters, isolation cells and retention flops are required. It describes how power is switched on and off to the various power domains.
Power intent can be captured in several ways
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Through explicit definition in the RTL by hand instantiating the level shifters, isolation cells, etc.
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Through explicit definition in the RTL by using HDL pragmas.
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Through the use of tool-specific commands.
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Through the use of a accompanying power file in a standard format such as the Unified Power Format (UPF).
For the purposes of the discussion here, we will use the UPF format.
11.3.2 Defining Power Domains and Power Connectivity
In UPF, power domains are specified with the following command.
<b class="bold">create_power_domain</b> <i class="emphasis">domain_name</i> [-<b class="bold">elements</b> <i class="emphasis">list</i>] [<b class="bold">-include_scope</b>] ...
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