Low Power Methodology Manual: For System-on-Chip Design
Taking a practical approach, rather than a theoretical approach, this book describes a number of the techniques designers can use to reduce the power consumption of complex SoC designs.
TABLE OF CONTENTS Low Power Methodology Manual: For System-on-Chip Design
11.2: Design Flow Overview
11.2 Design Flow Overview
As show in Figure 11-4, the design flow for a multi-voltage, power gating design follows that of a standard implementation with a few exceptions.
Figure 11-4: Design Flow Overview
Primarily, the differences between the standard design flow and that for a multi-voltage, power gated design are:
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Specification of the power intent
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Creation of power domains during synthesis
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State retention synthesis with always-on network management
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Multi-voltage physical design partitioning and the addition of MTCMOS switch cells
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Multi-voltage power network synthesis for MTCMOS power gating during power planning phase
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Early power network analysis to validate power gating switch topology
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Multi-voltage placement optimization including level shifter and isolation cell optimization
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Multi-voltage clock tree synthesis and optimization
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Intensive post route power network analysis with power-up sequencing verification
Copyright Synopsys, Inc. & ARM Limited 2007 under license agreement with Books24x7
