Overview

The previous chapters have discussed low power design from the perspective of the system architect and chip designer. This chapter describes low power design from the perspective of the engineers who design complex IP, such as processors, DSPs, USB, PCI Express, and bus infrastructure. Until now, we have assumed that the IP is relatively fixed, and that we must add low power capability to it. Now we discuss how to design complex IP to meet our low power objectives.

Today the vast majority of complex chips are designed using IP either third party or internally developed. And the key to designing good IP is to design it in a way that allows it to be used in multiple applications.

To assure that an IP can be used effectively in multiple applications requiring low power, we must design it so that it can be used with different power strategies. In one application, clock gating and multiple V _T libraries may provide low enough power. In other applications, aggressive on-chip power gating may be required. In other applications, dynamic voltage scaling may be the key to achieving the chip's power goals.

To address these various needs, we need to do the following:

• Partition the design to support various low power strategies, especially power gating

• Include explicit support for power gating

• Develop reference power intent files

• Design the clocking and reset strategy with low power in mind

• Package the IP to support low power

• Verify the IP using various low...