TABLE OF CONTENTS Over the past three decades, we have seen the semiconductor manufacturing technology advance from 4 microns to 45 nanometers. This shrinkage of feature size has made a dramatic impact on design and test. Now we find system-on-chip (SOC) and system-in-package (SIP) designs that embed more than 100 million transistors running at operating frequencies in the gigahertz range. Within this decade, there will be designs containing more than a billion transistors. These designs can include all varieties of digital, analog, mixed-signal, memory, optical, microelectromechani-cal systems (MEMS), field programmable gate array (FPGA), and radiofrequency (RF) circuits. Testing designs of this complexity is a significant challenge, if not a serious problem. Data have shown it is beginning to require more than 20% of the development time to generate production test patterns of sufficient fault coverage to detect manufacturing defects.
Additionally, when the SOC design is operated in a system, soft errors induced by alpha-particle radiation can adversely force certain memory cells or storage elements to change their states. These soft errors can cause the system to malfunction. As complementary metal oxide semiconductor (CMOS) scaling continues, the combined manufacturing defects and soft errors start to threaten the practicality of these nanometer SOC designs.
In this chapter, we first describe the importance of SOC testing and review the design and...
