TABLE OF CONTENTS As complementary metal oxide semiconductor (CMOS) devices are scaled down into the nanometer regime, new challenges at both the device and system levels are arising. Many of these problems were discussed in the previous chapters. Though the semiconductor industry and system designers will continue to find innovative solutions to many of these problems in the short term, it is essential to investigate CMOS alternatives. New devices and structures are being researched with vigor within the device community. They include resonant tunneling diodes, quantum-dot cellular automata, silicon nanowires, single electron transistors, and carbon nanotubes. Each of these devices promises to overcome the fundamental physical limitations of lithography-based silicon (Si) very-large-scale integration (VLSI) technology.
Although it is premature to predict which device will emerge as a possible candidate to either replace or augment CMOS technology, it is clear that most of these nanoscale devices will exhibit high defect rates. Consequently, one key question system designers will have to address is how to build reliable circuits, architectures, and systems from unreliable devices. New testing and defect tolerance methodologies at all levels of the design hierarchy will be needed to target these devices.
The focus of this chapter is to provide a brief overview of test technology trends for circuits and architectures composed of some of these emerging nanoscale devices. In particular, defect characterization, fault...
