System-on-Chip Test Architectures: Nanometer Design for Testability

The scale of analog integrated circuits (ICs) and the analog portion of mixed-signal ICs is usually relatively small compared to digital IC counterparts hundreds of devicesin an analog circuit compared to millions tohundreds of millions of devices in a digitalcircuit. However, testing analog circuits poses a number of unique testing problemswhen compared to digital circuits and, as a result, requires a variety of different and uniquetest architectures and approaches. For example, there are no analog fault models that have been widely accepted, as is the case in digital testing. As a result, most analog testing tends to be specification-oriented as opposed to defect-oriented approaches typically used when testing digital circuitry. This is due in part to the fact that there is a range of good circuit signal values that result from acceptable component tolerances, environmental variations (including temperature and supply voltage), and noise.
An introduction to analog and mixed-signal testing was given in [Wang 2006], and a number of exceptional books have been dedicated to testing analog and mixed-signal circuits, including [Burns 2000], [Mahoney 1987], [Roberts 1995], and [Vinnakota 1998]. Therefore, this chapter begins with an overview of some of the challenges in analog and mixed-signal testing followed by a discussion of some fundamental analog test techniques and measurements. The chapter then focuses on test architectures that can be included for on-chip test and measurement of the analog portion(s) of system-on-chip (SOC) implementations.