TABLE OF CONTENTS Advances in semiconductor manufacturing technology have allowed the integration of a billion transistors in a nanometer design. The nanometer design has faced many test challenges [SIA 2005, 2006]. Growing complexity and defect mechanisms of fabricating the nanometer design have made the circuit even more vulnerable than earlier generations to physical failures caused during manufacturing and susceptible to radiation during system applications. In this chapter, we first presented several promising techniques for testing nanometer designs that can cope with physical failures caused by signal integrity, defects, and process variations during manufacturing. These test techniques are developed for reliability screen or DPM reduction. A few include on-chip hardware for stressing or special reliability measurements. These defect avoidance techniques are generally referred to as design for manufacturability (DFM).
With the process node now scaling down to 65 nanometers and below, DFM alone is not enough. Many new defect mechanisms, such as copper-related defects and defects as a result of optical effects, become much more likely [Gizopoulos 2006]. Any single-event upsets can increase logic and memory soft error rates. It is thus becoming crucial to ensure that the chips can still function at the end system in the presence of these defects and soft errors, especially when the chips are to be installed into airplanes, pacemakers, or cars for safety-critical concerns. This chapter then further covered a number of error-resilient and defect-tolerant designs embedded on-chip to tolerate soft errors and defects. Although these schemes may require additional area overhead, they...
