TABLE OF CONTENTS Delay testing is used to verify that a circuit meets its timing specifications. This chapter introduces delay testing of digital logic in synchronous circuits and then focuses on delay tests that target the circuit structure. Approaches for applying delay tests in scan designs are first discussed, including issues in clocking. Delay fault models are then described along with their sensitization criteria. The chapter includes a discussion of recent research in defect-based delay fault models.
The second half of the chapter discusses delay fault simulation and automatic test pattern generation. Delay fault simulation is used to grade the coverage of functional test patterns, as well as to drop faults that are fortuitously detected while targeting other faults.
Through this chapter, the reader will learn about the major delay fault modeling, simulation, and test generation techniques and their application to modern digital circuits. This background will be valuable for selecting the delay test methodology that best meets the design needs.
Timing is one of the specifications that must be verified during digital circuit testing. This type of test is referred to as a delay test. Sometimes delay testing is referred to as AC testing to distinguish it from the DC test conditions of stuck-at faults. Delay testing is becoming increasingly important, as timing margins are reduced to maximize performance while minimizing power dissipation.
There are three basic approaches to...
