TABLE OF CONTENTS Regardless of how complex a semiconductor device or chip is, the first thing that has to be dealt with is its pins or input/output (I/O) interfaces. They can be connected and probed by a myriad set of instruments. From a test perspective, because these pins often are visible, they also carry complex specifications such as drive/sense levels, source/sink capability, leakage, etc. As the signaling rate of a device goes up, more of its signaling characteristics also are specified. This is evident by picking up any datasheet of a chip/component. As processor speed continues to increase, I/O has become the bottleneck, constraining system-level performance. A processor may compute very fast, but if the instructions and data do not reach the processor in time, it simply has to wait. Therefore, improving I/O performance is essential for improving system-level performance. Consequently, in current systems, I/O has become the most important element requiring special attention.
This chapter is devoted to high-speed parallel/serial I/O link testing at both chip and system levels. It starts with a discussion of various I/O architectures and then explores various test methodologies for them. In particular, we conduct an extensive overview of the signaling properties of high-speed serial I/O, including jitter, noise, and bit error rate (BER). We also present design-for-testability-assisted (DFT-assisted) test methods for manufacturing test. Novel DFT...
