TABLE OF CONTENTS Since the early 1980s, complementary metal oxide semiconductor(CMOS) process has become the dominant manufacturing technology. At the introduction rate of a new process technology (node) roughly every 2 years, which is a reflection of the Moore's law [Moore 1965], new defect mechanisms have initially caused low manufacturing yield, elevated infant mortality rates, and high defect levels. As CMOS scaling continues (down to a feature size of 65 nanometers and below), additional defect mechanisms caused by new manufacturing defects (such as defects as a result of optical effects) and process variations continue to create various failure mechanisms. To meet yield, reliability, and quality goals (referred to as defective parts per million[DPM]), these defects must be screened during manufacturing or be tolerated during system operation.
Defects are physical phenomena that occur during manufacturing and can cause functional or timing failures. Examples of defects are missing conducting material or extra insulating material (possibly causing opens), the presence of extra conducting material, or missing insulating material between two signal lines (possibly causing shorts), among others. A defect does not always manifest itself as a single isolated problem such as an open or a short. When a circuit parameter is out of given specifications, it can also cause a failure or become susceptible to other problems (temperature effects, crosstalk, leakage power, etc.). New manufacturing processes, such as a changeover from aluminum metallization to copper metallization and from Si0 2 to low-K interlayer dielectric [Tyagi 2000], have...
