TABLE OF CONTENTS Since the 1980s, we have seen the emergence and rapid growth of system-on-chip (SOC) applications. The same trend has happened in system-in-package (SIP) applications since the mid-1990s. The development of SIP technology has benefited from the SOC technology; however, this emerging SIP technology presents specific test challenges because of its complex design and test processes. Indeed, one major difference between an SOC and an SIP is that an SOC contains only one die on a packaged chip whereas an SIP is an assembled system composed of a number of individual dies on a packaged chip. Each die in the SIP can also use a different process technology, such as silicon or gallium-arsenide (GaAs), which includes a radiofrequency (RF) or microelectromechanical systems (MEMS) components. This fundamental difference implies that to test an SIP, each bare die in the SIP must be tested first before the bare die is packaged in the SIP. Then, a functional system test or embedded component test at the system level can be performed. The passing bare dies are often called known-good-die (KGD).
In this chapter, we first discuss the basic SIP concepts, explore SIP technology's difference from the SOC technology, and show some SIP examples. We highlight the specific challenges from the testing point of view...
