TABLE OF CONTENTS Designers have to be prepared for the scenario where chips do not work as intended or do not meet performance expectations after they are fabricated. Product yield engineers need to know what has caused their product yield to be below expectation. Reliability engineers need to know what circuits or elements have failed from various stresses and which ones customers have returned. It is necessary to debug and diagnose chip failures to find the root cause of these issues, and this is best facilitated if the design has accommodated features for debug and diagnosis.
This chapter focuses on the design features at the architectural, logic, circuit, and layout level that are needed to facilitate silicon debug and defect diagnosis of integrated circuits. These design features are generally referred to as design for debug and diagnosis (DFD). We explain how these DFD features are used effectively in a debug or diagnosis environment for applications ranging from design validation, low-yield analysis, and all the way to field failure analysis. Common probing techniques used to access internal signal values (logic and timing) and alter the execution and timing behavior of an integrated circuit in a controlled manner are covered. We also describe circuit editing techniques and tools to enable probing, validate hypotheses, and confirm root-cause design fixes. These DFD features are categorized into logic DFD (LDFD) features, which enable the nonintrusive isolation of failures, and
