TABLE OF CONTENTS With the advances in semiconductor manufacturing technology, the concept of system-on-chip (SOC) has become a reality. An SOC device can contain a large number of complex, heterogeneous components including digital, analog, mixed-signal, radiofrequency (RF), micromechanical, and other systems on a single piece of silicon. The increasing heterogeneity and programmability of the SOC, along with the ever-increasing frequency and technology changes, however, are posing serious challenges to manufacturing test and on-chip self-test. Scan testing is the most commonly used design-for-testability (DFT) technique to address the fault coverage and test cost concerns. The problem is lacking self-test ability in the field. Hardware-based structural self-test techniques, such as logic built-in self-test (BIST), offer a feasible solution. Many solutions have been developed over the years to increase a circuit's fault coverage while reducing area overhead and development time. However, structural BIST usually places the circuit in specific self-test mode. Like scan testing, it may also cause excessive test power consumption, overtesting, and yield loss.
Software-based self-testing (SBST) has attracted much attention to address those problems caused by structural BIST. The idea is to utilize on-chip programmable resources such as embedded processors for on-chip functional (rather than structural) test pattern generation, test data transportation, response analysis, and even diagnosis. In this chapter, we present a variety of methods for SBST. We start by discussing processor self-test techniques followed by a brief...
