TABLE OF CONTENTS Design for testability (DFT) has become an essential part for designing very-large-scale integration (VLSI) circuits. The most popular DFT techniques in use today for testing the digital logic portion of the VLSI circuits include scan and scan-based logic built-in self-test (BIST). Both techniques have proved to be quite effective in producing testable VLSI designs. Additionally, test compression, a supplemental DFT technique to scan, is growing in importance for further reducing test data volume and test application time during manufacturing test.
To provide readers with an in-depth understanding of the most recent DFT advances in scan, logic BIST, and test compression, this chapter covers a number of fundamental and advanced digital test architectures to facilitate the testing of modern digital circuits. These architectures are required to improve the product quality and reduce the defect level, test cost, and test power of a digital circuit while at the same time simplifying the test, debug, and diagnosis tasks.
In this chapter, we first describe fundamental scan architectures followed by a discussion on advanced low-power and at-speed scan architectures. Next we present a number of fundamental and advanced logic BIST architectures that allow the digital circuit to perform self-test on-chip, on-board, or in-system. We then discuss test compression architectures designed to reduce test data volume and test application time. This includes a description of advanced low-power and at-speed test compression architectures practiced in industry. Finally, we...
