8.1

(Signal Integrity) Figure 8.10 shows one readout circuit for reading the signal integrity loss information through a scan chain. How do you change this architecture to achieve the following?

1. Less integrity test overhead.

2. More accuracy in terms of pinpointing the problematic wire/bus.

   In each case, draw your architecture and estimate the duration of the signal integrity test session.

8.2

(Signal Integrity) For the equation given in Section 8.2.3 that approximates the frequency of a ring oscillator, do the following:

1. Use a partial derivative to analytically determine the sensitivity of fR0 with respect to Vt and T _ox.

2. Use the library and technology parameters available to your SPICE tool, replace the subset of parameters needed, and find the frequency shift for a 15% increase of Vt and a 20% reduction in T _ox.

3. Run SPICE for the same variations, and compare the frequency shift with the analytical results found in part (b).

8.3

(Memory Repair) What is the minimum cost of using Hamming ECC (a single-bit error correction and double-bit error detection code) to protect a 64-bit-wide memory word ( e.g., the number of check bits over the number of 64-bit word)?

8.4

(Redundancy) What is the marginal increase of redundancy if the number of redundant elements (rows, columns, or blocks) increases by 2x? (Hint: You have to look at the yield decrease because the area has increased by 2x.)

8.5

(Adaptive Design)