TABLE OF CONTENTS A couple of tolerance terminologies have surfaced: defect tolerance [Koren 1998] and error tolerance [Breuer 2004a, 2004b]. Defect tolerance requires inserting redundancy circuitry in a circuit under test so the circuit can continue correct operation in the presence of defects. An example is adding self-diagnosis and self-repair circuitry or error-correcting code (ECC) to ensure correct memory operation. Error tolerance, on the other hand, allows the circuit to continue acceptable operation in the presence of errors. An example is the MPEG player where a pixel may be faulty but the player can continue acceptable operation.
In the nanometer design era, the International Technology Roadmap for Semiconductors (ITRS) has indicated that the efforts in fabricating a defect-free chip can be extremely expensive [SIA 2006]. Consider random spot defects. Assume a design consists of N submodules each having n unique positions where a defect would cause it to fail its tests. There are D defects uniformly distributed over the submodule such that each defect lands at a unique position. In addition, assume that the number of defects in any submodule is independent of the number of defects in other submodules. The authors in [Breuer 2004a] conducted an analysis of defect probability and showed that the probability that an arbitrary position on a submodule is associated with a defect isp =D/(nN), and the probability of having d defects in a given submodule is:
where C(n,d) = n!/(d!(n ...
