TABLE OF CONTENTS The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, long test development and test application times, and high test data volumes. The on-chip network is a natural evolution of traditional interconnects such as shared bus. An SOC whose interconnection is implemented by an on-chip network is called a network-on-chip (NOC) system. Testing an NOC is challenging, and new test methods are required.
This chapter presents techniques that facilitate low-cost modular testing of SOCs. Topics discussed here include techniques for wrapper design, test access mechanism optimization, test scheduling, and applications to mixed-signal and hierarchical SOCs. Recent work on the testing of embedded cores with multiple clock domains and wafer sort of core-based SOCs are also discussed. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test cost. The discussion is then extended to the testing of NOC-based designs. Topics discussed here include reuse of on-chip network for core testing, test scheduling, test access methods and interface, efficient reuse of the network, power-aware and thermal-aware testing, and on-chip network (including interconnects, routers, and network interface) testing. Finally, two case studies, onefor SOC testing and the other for NOC testing, are presented based on industrial chips developed by Philips.
