The authors wish to thank Professor Yiorgos Makris of Yale University for contributing the Circuit-Level Approaches in the Soft Errors section; Professor Mohammad Tehranipoor of University of Connecticut and Professor Saraju P. Mohanty of University of North Texas for reviewing the Signal Integrity section; Dr. Jonathan T.-Y. Chang of Intel, Fran?ois-Fabien Ferhani of Stanford University, Professor James C.-M. Li of National Taiwan University, Praveen K. Parvathala and Michael Spica of Intel, Professor Michael S. Hsiao of Virginia Tech, Phil Nigh of IBM, and Dr. Brion Keller of Cadence Design Systems for reviewing the Structural Tests and Defect-Based Tests sections; Praveen K. Parvathala and Dr. Li Chen of Intel for reviewing the Functional Tests section; Dr. Shih-Lien Lu of Intel for reviewing the Process Sensors and Adaptive Design section; Professor Subhasish Mitra of Stanford University for reviewing the Soft Errors section; Professor Kuen-Jong Lee of National Cheng Kung University and Michael Spica of Intel for proofreading the Defect and Error Tolerance section; Professor Shi-Yu Huang of National Tsing Hua University and Dr. Srikanth Venkataraman of Intel for providing helpful comments; as well as Teresa Chang of SynTest Technologies for drawing most of the figures.