TABLE OF CONTENTS Physical failures caused by manufacturing defects and process variations, as well as soft errors induced by alpha-particle radiation, have been identified as the main source of faults attributed to chip or system failure. Today, the semiconductor industry relies heavily on two test technologies: scan and built-in self-test (BIST). Existing scan implementations may no longer be sufficient as scaling introduces new failure mechanisms that exceed the ability to capture by single-fault-model-based tests. BIST will also become problematic if it does not achieve sufficient fault coverage in reasonable time. Faced with significant test problems in the nanometer design era, it is imperative that we seek viable test solutions now to complement the conventional scan and BIST techniques.
In this chapter, we focus on test techniques to cope with physical failures for digital logic circuits. Techniques for improving process yield, silicon debug, and system diagnosis, along with test methods and DFT architectures for testing field programmable gate array (FPGA), microelectromechanical systems (MEMS), and analog and mixed-signal (AMS) circuits are covered in subsequent chapters. In this chapter, we first discuss test techniques to deal with signal integrity problems. We then describe test techniques to screen manufacturing defects and process variations. Finally, we present a number of promising online error-re si lient architectures and schemes to cope with soft errors as well as...
