TABLE OF CONTENTS This chapter we looks at some of the formal definitions of the Verilog language: identifiers, white space, comments, numbers, text macros, modules, value set, and strengths.
Identifiers are the names Verilog uses for the objects in a design. Identifiers are the names you give your wires, gates, functions, and anything else you design or use. The basic rules for identifiers are as follows:
May contain letters (a-z, A-Z), digits (0-9), underscores (_), and dollar signs ($).
Must start with a letter or underscore.
Are case sensitive (unless made case insensitive by a tool option).
May be up to 1024 characters long.
Other printable ASCII characters may be used in an escaped identifier.
What this means is that you are not limited to eight or sixteen characters to name things. You have over a thousand characters to use in the name of an identifier, so use names that make sense to you. Because names can start with a letter or underscore, and can contain letters and digits, you have quite a bit of flexibility.
Verilog does not have a standard notation for negated or active low signals. In this book, the standard for active low signals will be the name of the signal followed by _ n. We use this notation to indicate active low signals because the notation is compatible with both Verilog and VHDL. (VHDL does not allow either leading or trailing underscores in names.) We make this recommendation to emphasize good habit from the beginning:...
