How do you figure out what is wrong when a difference occurs between a behavioral model and a gate-level model? How do you determine what is wrong when one behavioral model works and another one, which is supposedly equivalent, does not?

In such cases, one of the first things to check is timing. Are both models for the circuit expecting inputs at the same time? Are the inputs being provided at the proper times? Different models often have different output timing. A behavioral model might have zero or unit delay, but a gate-level model may have some longer delay associated with the actual gates. Is the circuit taking longer than expected by the test bench or other connection modules to produce correct outputs, or are you just looking for the outputs too soon?

Another common gate-level problem involves unknowns. Use the techniques shown earlier in this chapter to back-trace the source of any unknowns. If the unknowns lead back to flip-flops or registers, perhaps the these are not properly reset.

Another source of unknowns is differences in how certain conditions are handled. The behavioral model for a mux might have a known output when the two inputs are known, but the select might be unknown, and the gate-level model might pass the unknown to the output.

Unknowns may cause other types of mismatches. The pre-synthesis model may have used x to indicate a don't care condition to synthesis. After synthesis these x's will become