TABLE OF CONTENTS This chapter introduces the different types of data you can work with in Verilog: Nets, regs, integers, times, parameters, events, and strings.
Nets (sometimes called wires) are the most common data object in Verilog. Nets are used to interconnect modules and primitives, as discussed in Chapter 3. You used nets in Exercise 2. There are net types representing wired OR, wired AND, storage nodes, pullups, and pulldowns. The default net type is a plain wire with no special properties.
The net types are listed in Table 6-1.
| Net Type | Description |
|---|---|
| wire | Default net type, a plain wire |
| tri | Another name for wire |
| wand | Wired AND |
| triand | Another name for wand |
| wor | Wired OR |
| trior | Another name for wor |
| tri1 | Wire with built-in pullup |
| tri0 | Wire with built-in pulldown |
| supply1 | Always 1 |
| supply0 | Always 0 |
| trireg | Storage node for switch-level modeling |
wire is the default net type. You can change the default net type to one of the other types, but most nets are of type wire. wire and tri are the same type of net. The reason for having two names for this type of net is that some people may want to distinguish in their designs those nets that are expected to tri-state from those that do not. You can use tri to distinguish a net that you expect to have high impedance values or multiple drivers. If two drivers are driving a net of...
