TABLE OF CONTENTS Throughout this book modeling concepts have been presented without particular attention to organization of the models.
You may have noticed that the examples on CDROM with this book are in files where the file name matches the module name. It is standard practice to have only one module in a file and to give the file the same name as the module, with .v appended.
Verilog simulators allow you to supply a list of files to simulate. As you build more complex circuits, the file list is a way to organize your design. For example the 8 bit adder design should be in 5 files as shown in Example 19-1. For many tools you can create a text file with the list of files. This list is often suffixed with . vc (verilog commands) or . f (file). Many simulators accept this list of files by using a - f option, as in Example 19-2. The Silos simulator included with this book includes a project manager where you specify the files in your project.
<a name="810"></a><a name="page264"></a>adder1.vadder2.vadder4.vadder8.vtest_adder.v
verilog -f adder.vc
Simply listing the design files is not the only organizational trick you can use. Verilog includes an include compile directive. The include in verilog is similar to the #include in C . It allows another file to be part of the current file. It is...
