TABLE OF CONTENTS Most circuits are either sequential or combinatorial. The Verilog constructs can be used to model both combinatorial and sequential circuits, and it is possible to create models in Verilog that are neither combinatorial or sequential. (However, if a model is neither sequential nor combinatorial it may not be possible to built it in actual hardware.) This chapter provides modeling rules for both combinatorial as well as sequential circuits.
In addition to presenting styles for combinatorial and sequential circuits, this chapter presents tips for synchronous and asynchronous circuits such as one-shots, and special-purpose models such as two-dimensional arrays.
Combinatorial logic is always synthesizable. What Verilog constructs can you use for combinatorial logic? You can use nets ( wire, tri, tril, tri0, trior, wand, etc.) for modeling combinatorial logic. You can even use Verilog regs for modeling combinatorial logic!
What constructs can you use to assign a value to a net? You can only use the continuous assignment. The continuous assignment always models combinatorial logic. (There is one exception, which is shown in Example 16-5.) Example 16-1, Example 16-2, Example 16-3 and Example 16-4 show simple, common combinatorial circuits.
module mux2ca ( y, sel, a, b);output [3:0] y;input [3:0] a, b;input sel;assign y = sel? a: b;endmodule
Example 16-1 shows a 2-to-1 mux modeled with a continuous assignment. One advantage of this model is that it could be used to model...
