TABLE OF CONTENTS So far you have learned structural modeling and enough high level code to apply stimulus and to display results from your circuits. You have also read about Verilog's rich set of operators and data objects to use as operands. In this chapter you will learn how to use the operators to model circuits at a higher level of abstraction than merely structural. At the end of chapter 10 is an exercise based on the operators introduced in Chapter 8, and the high level constructs presented in this chapter.
The continuous assignment is the simplest of the high level constructs. A continuous assignment is just like a gate: It drives a value out onto a wire. A continuous assignment is different from a procedural assignment in a few ways. First, the destination (left-hand side, or LHS) is always a wire. Second, the continuous assignment is automatically evaluated when any of the operands change. Unlike a procedural assignment, the continuous assignment cannot occur in a block of sequential code. The continuous assignment is always a module item by itself. Finally, a continuous assignment always models combinatorial logic. It is true that you can create logic that feeds back into itself and mimics storage, but still it is combinatorial.
Example 9-1 shows a simple 16-bit, three-state buffer using a continuous assignment.
module buf16 (out, in, enable); // 16-bit, three-state bufferinput [15:0] in;output [15:0] out;input enable;assign out = enable...
