Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

There are two types of state machines: Mealy machines and Moore machines. You can model both types of machines in Verilog. The difference between Mealy and Moore machines is in how outputs are generated. In a Moore machine, the outputs are a function of the current state. This implies that the outputs from the Moore machine are synchronous to the state changes. In a Mealy machine, the outputs are a function of both the state and the inputs.
A state machine can be broken down into three parts: The state register, the next-state logic, and the output logic.
A state machine can be depicted as shown in Figure 15-1.
Figure 15-1 can be modified to bring the inputs through to the output logic, thus creating a Mealy state machine, as shown in Figure 15-2.
To model a state machine in Verilog, you must model each of the three parts of the state machine.
Because a state machine is made up of three parts, you have a choice whether to model each section independently, or to try to combine the parts into one section of the model.
Table 15-1 shows some interesting combinations:
| Style | State Register | Next-State Logic | Output Logic |
|---|---|---|---|
| 1 | Separate | Separate | Separate |
| 2 | Combined | Combined | Separate |
| 3 | Separate | Combined | Combined |
| 4 | Combined | Combined | Combined |
| 5 | Combined | Separate | Combined |
In the first style, each of the functional...