TABLE OF CONTENTS The data types reg, integer, real, and time can only be assigned values in procedural blocks of code. These assignments are called procedural assignments. They are similar to variable assignments in other programming languages. When the statement is executed, the variable on the left-hand side of the assignment receives a new value.
The destination of a procedural assignment is never a wire. The procedural assignment is one of three types of assignments you will learn in Verilog. For now, just remember that the left-hand side of a procedural assignment is a reg. The left-hand side can contain an integer, time, or real, but these data types can be thought of as abstractions of regs.
There are three varieties of the procedural assignment: The simple procedural assignment, the procedural assignment with an intra-assignment delay, and the nonblocking procedural assignment, all of which are described in this section.
<a name="262"></a><a name="IDX-74"></a>module ia;integer i, j;reg [7:0] a, b;initial begin i = 3; j = 4; a = i + j; b = a + 1; #10 i = a; j = b;end endmodule
In Example 7-1, the first four assignments occur at time 0, followed by a delay of 10 time units, and then the last two assignments take place. This example shows how an assignment can have no delay or...
